While form factors continue to shrink in size, consumer demand for faster processing speeds and increased memory capacity in mobile devices continues to rise. Recently, the IC industry has begun to practice three-dimensional (3D) integration of flip chip packages and peripheral devices using package-on-package (PoP) or direct die-to-die interconnection with through silicon vias (TSVs). However, currently available technologies do not provide for the use of thinner package substrates such as bumpless build-up layers in 3D integration schemes.